XCV300E-6BG240C PDF Datasheet
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Description
This is Virtex-E 1.8 V Field Programmable Gate Arrays. 0
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Virtex™-E 1.8 V Field Programmable Gate Arrays
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DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
Features
Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MH- internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.3 V, 32, 64-bit, 33, 66-MH- Highly Flexible SelectI, O+™ Technology - Supports 20 high-performance interface standards - Up to 804 singled-ended I, Os or 344 differential I, O pairs for an aggregate bandwidth of > 100 Gb, s Differential Signalling Support - LVDS (622 Mb, s), BLVDS (Bus LVDS), LVPECL - Differential I, O signals can be input, output, or I, O - Compatible with standard differential devices - LVPECL and LVDS clock inputs for 300+ MH- clocks Proprietary High-Performance SelectLink™ Technology - Double Data Rate (DDR) to Virtex-E link - Web-based HDL generation methodology Sophisticated SelectRAM+™ Memory Hierarchy - 1 Mb of internal configurable distributed RAM.