QS5LV91970J PDF Datasheet
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Description
This is 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER. QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES: DESCRIPTION:
QS5LV919
3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0 Q4 2xQ output, Q outputs, Q output, Q, 2 output Outputs 3-state and reset while OE, RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to MC88LV915, IDT74FCT388915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MH- maximum frequency (2xQ output) Available in QSOP and PLCC packages
The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q 0-Q 4, Q5, Q, 2. Careful layout and design ensure < 300 ps skew between the Q 0-Q 4, and Q, 2 outputs. The QS5LV919 includes an .