K4S561632D PDF Datasheet
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Description
This is 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL.
K4S561632D
CMOS SDRAM
256Mbit SDRAM
4M x 16bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.1 Aug. 2002
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Aug. 2002
K4S561632D
Revision History Revision 0.0 (Jan., 2002)
-First generation
CMOS SDRAM
Revision 0.1(Aug.,2002)
- ICC6 of Low power is changed from 1.0 to 1.5 due to typo.
Rev. 0.1 Aug. 2002
K4S561632D
4M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-b.