CYS25G0101DX PDF Datasheet
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Description
This is SONET OC-48 Transceiver.
CYS25G0101DX
SONET OC-48 Transceiver
Features
SONET OC-48 operation Bellcore and ITU jitter compliance 2.488-GBaud serial signaling rate Multiple selectable loopback, loop-through modes Single 155.52-MH- reference clock Transmit FIFO for flexible data interface clocking 16-bit parallel-to-serial conversion in transmit path Serial-to-16-bit parallel conversion in receive path Synchronous parallel interface LVPECL-compliant data recovery operations in a single chip, optimized for full SONET compliance. Transmit Path New data is accepted at the 16-bit parallel transmit interface at a rate of 155.52 MHz. This data is passed to a small integrated FIFO to allow flexible transfer of data between the SONET processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out the high-speed differential line driver at a rate of 2.488 Gbits, second. Receive Path As serial data is received at the differenti.