AD6641 PDF Datasheet
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Description
This is 250 MHz Bandwidth DPD Observation Receiver.
250 MH- Bandwidth DPD Observation Receiver AD6641
FEATURES
SNR = 65.8 dBFS at fIN up to 250 MH- at 500 MSPS ENOB of 10.5 bits at fIN up to 250 MH- at 500 MSPS ( 1.0 dBFS) SFDR = 80 dBc at fIN up to 250 MH- at 500 MSPS ( 1.0 dBFS) Excellent linearity DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical Integrated 16k × 12 FIFO FIFO readback options 12-bit parallel CMOS at 62.5 MH- 6-bit DDR LVDS interface SPORT at 62.5 MH- SPI at 25 MH- High speed synchronization capability 1 GH- full power analog bandwidth Integrated input buffer On-chip reference, no external decoupling required Low power dissipation 695 mW at 500 MSPS Programmable input voltage range 1.18 V to 1.6 V, 1.5 V nominal 1.9 V analog and digital supply operation 1.9 V or 3.3 V SPI and SPORT operation Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment
GENERAL DESCRIPTION
The AD6641 is a 250 MH- bandwidth digital predistortion (DPD) observation receiver that int.