74HCT138 PDF Datasheet
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Description
This is 3-to-8 line decoder/demultiplexer inverting. INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC, HCT, HCU, HCMOS Logic Family Specifications The IC06 74HC, HCT, HCU, HCMOS Logic Package Information The IC06 74HC, HCT, HCU, HCMOS Logic Package Outlines
74HC, HCT138 3-to-8 line decoder, demultiplexer; inverting
Product speci cation File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product speci cation
3-to-8 line decoder, demultiplexer; inverting
FEATURES Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC, HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
74HC, HCT138
The 74HC, HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enable.