74HC10 PDF Datasheet


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Description

This is Triple 3-input NAND gate. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC, HCT, HCU, HCMOS Logic Family Specifications The IC06 74HC, HCT, HCU, HCMOS Logic Package Information The IC06 74HC, HCT, HCU, HCMOS Logic Package Outlines 74HC, HCT10 Triple 3-input NAND gate Product speci cation File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product speci cation Triple 3-input NAND gate FEATURES Output capability: standard ICC category: SSI GENERAL DESCRIPTION 74HC, HCT10 The 74HC, HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC, HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL, tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where: fi = input frequency in .