74F109 PDF Datasheet
Please enter the part number you wish to PDF download in the search bar.
Description
This is Positive J-K positive edge-triggered flip-flops. INTEGRATED CIRCUITS
74F109 Positive J-K positive edge-triggered flip-flops
Product specification IC15 Data Handbook 1990 Oct 23
Philips Semiconductors
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
FEATURE
Industrial temperature range available ( 40°C to +85°C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows.